DSP Builder for Intel® FPGAs (Advanced Blockset): Handbook

ID 683337
Date 6/20/2022

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Document Table of Contents

11.7.1. Implementing the Newton Design


  1. Add and connect the blocks in the Newton design.
  2. Reduce logic usage by configuring the Mult, Add, Sub, and Divide blocks to use faithful rounding.
  3. Create the iteration loop by feeding back the output guess to the input guess through a SampleDelay block. The design detects when a sample finishes iterating by comparing the residue with zero.
  4. Ensure that the length of this delay is sufficiently large so that the scheduling succeeds.
  5. Turn on the SampleDelay block Minimum delay parameter so that DSP Builder determines this length automatically.