DSP Builder for Intel® FPGAs (Advanced Blockset): Handbook

ID 683337
Date 6/20/2022

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7.5. DSP Builder Finite State Machine Design Example

The Finite State Machine example design demonstrates some of the features of the finite state machine (FSM) specification and its function in a primitive subsystem. The example first selects 20 odd numbers from the output of the counter block and then selects 8 multiples of 4 from that same counter. The model file is demo_fsm.mdl.
Figure 51. Example
# example 0
inputs odd four
enable ena
start go
for x 20 > 0 step -1
    transitions oddWait 
        finish fin
        state _init
            if (~odd) hold
        state hold
            if (odd) _init

# for loop specifies its counter as an output port
for x 0 < 8 : c
    # state transitions declare an output named q
    transitions fourWait : q
        # state transition back to _init state will 
        #output a pulse on port named tko
        finish tko
        state _init
            if (~four) hold 1
        state hold
            if (four) _init 0

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