DSP Builder for Intel® FPGAs (Advanced Blockset): Handbook

ID 683337
Date 6/20/2022

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7.3.2. Building the DDC Design Example


  1. Open the model, by typing the following command in the MATLAB window:
    demo_ddc r
  2. Simulate the design example in Simulink, by typing the following command in the MATLAB window:
    sim('demo_ddc', 550000.0*demo_ddc.SampleTime);
    Figure 46. Simulation Results Shown in the IScope BlockThe IScope block shows the first two channels (1 real and 1 complex for the first carrier) of data (magenta and yellow) as the input signals. The first trace shows the rapidly changing input signal that the testbench generates. The second signal shows the result of the mixer. This slowly changing signal contains the information to be extracted, plus a lot of high frequency residue. Applying the series of low-pass filters and decimating results in the required data.
    Note: If you turn on the Generate Hardware option in the parameters for the Control block, every time the simulation runs, DSP Builder synthesizes the underlying hardware, and writes out VHDL into the directory you specify.
  3. Simulate the generated RTL in the ModelSim simulator.
  4. Synthesize and fit the RTL in the Quartus Prime software.

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