DSP Builder for Intel® FPGAs (Advanced Blockset): Handbook

ID 683337
Date 6/20/2022
Public

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15.6.14. Variable Super-Sample Delay (VariableDelay)

The DSP Builder VariableDelay blocks provides a sample delay for super-sample data where multiple data samples arrive per clock cycle. For multiple data per clock cycle, a delay of one sample shifts the signals across the wires, and uses a register delay for just the one signal that wraps round to the beginning on the next cycle.

For example:

[1 2 3 4]' [5 6 7 8]' [9 10 11 12]'...

when delayed by one sample becomes

\n[X 1 2 3]' [4 5 6 7]' [8 9 10 11]' [12 ...

when delayed by two samples becomes

[X X 1 2]' [3 4 5 6]' [7 8 9 10]' [11 12 ...

where [1 2 3 4]' means 1,2,3 and 4 arrive in parallel on 4 separate wires. The Phases parameter specifies the number of parallel data samples The delay input must be a unsigned integer less than the number of parallel data samples.