DSP Builder for Intel® FPGAs (Advanced Blockset): Handbook

ID 683337
Date 6/20/2022

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7.13.6. 1-Carrier, 2-Antenna W-CDMA DDC

This reference design uses IP and Interface blocks to build a 4-channel, 2-antenna, single-frequency modulation DDC for use in an IF modem design compatible with the W-CDMA standard.

The top-level testbench includes Control, Signals, and Run Quartus Prime blocks, plus a ChanView block that isolates two channels of data from the TDM signals.

The DDCChip subsystem includes Device, DecimatingCIC, Decimating FIR, Mixer, NCO, and Scale blocks.

The CIC and FIR filters implement a decimating filter chain that down converts the two complex carriers (4 real channels from two antennas with one pair of I and Q inputs from each antenna) from a frequency of 122.88 MSPS to a frequency of 7.68 MSPS (a total decimation rate of 16). The real mixer and NCO isolate the four channels. The design configures the NCO with a single channel to provide one sine and one cosine wave at a frequency of 17.5 MHz. The NCO has the same sample rate (122.88 MSPS) as the input data sample rate.

A system clock rate of 122.88 MHz drives the design on the FPGA, which the Device block defines inside the DDCChip subsystem.

The model file is wcdma_picocell_ddc_mixer.mdl.

Note: This reference design uses the Simulink Signal Processing Blockset.