DSP Builder for Intel® FPGAs (Advanced Blockset): Handbook

ID 683337
Date 6/20/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

5.5. Simulating the RTL of the Fibonacci Design

Procedure

To verify that DSP Builder gives the same results when you simulate the generated RTL, click on the Run ModelSim block.
Figure 39. Fibonacci Sequence in the ModelSim Wave Window
Compile the design in the Quartus Prime software.