DSP Builder for Intel® FPGAs (Advanced Blockset): Handbook

ID 683337
Date 6/20/2022

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15.4.27. FIFO

The FIFO block models a FIFO memory. DSP Builder writes data through the d input when the write-enable input w is high. After some implementation-specific number of cycles, DSP Builder presents data at output q and the valid output v goes high. DSP Builder holds this data at output q until the read acknowledge input r is set high.

The FIFO block wraps the Intel single clock FIFO (SCFIFO) megafunction operating in show-ahead mode. That is, the read input, r, is a read acknowledgement which means the DSP Builder has read the output data, q, from the FIFO buffer, so you can delete it and show the next data output on q. The data you present on q is only valid if the output valid signal, v, is high

Table 196.  Parameters for the FIFO Block
Parameter Description
FIFO Setup A vector of three non-zero integers in the format: [<depth> <fill_threshold> <full_period>]
  • depth specifies the maximum number of data values that the FIFO can store.
  • fill_threshold specifies a low-threshold for empty-detection. If the number of data items in the memory is greater than the low-threshold, the t output is 1 (otherwise it is 0).
  • full_period specifies a high-threshold for full-detection If the number of data items is greater than the high-threshold, output f is 1 (otherwise it is 0).

If the inputs w or r is a vector, the FIFO setup parameter must be a three column matrix with the number of rows equal to the number of components in the vector. Each row in the matrix independently configures the depth, fill_threshold, and full_period of the FIFO buffer for the corresponding vector component.

Table 197.  Port Interface for the FIFO Block
Signal Direction Type Description Vector Data Support Complex Data Support
w Input Boolean Write enable. Yes No
d Input Fixed-point Data. Yes Yes
r Input Boolean Read acknowledge. Yes No
v Output Boolean Valid. Yes No
q Output Fixed-point Data. Yes Yes
t Output Boolean Fill threshold. Yes No
f Output Boolean Fullness. Yes No

You can to set fill_threshold to a low number (<3) and arrive at a state such that output t is high and output v is low, because of differences in latency across different pairs of ports—from w to v is 3 cycles, from r to t is 1 cycle, from w to t is 1 cycle. If this situation arises, do not send a read acknowledgement to the FIFO buffer. Ensure that when the v output is low, the r input is also low, otherwise a warning appears in the MATLAB command window. If the read acknowledgement is derived from a feedback from the t output, ensure that the fill_threshold is set to a sufficiently high number (3 or above). Likewise for the f output and the full_period.

You may supply vector data to the d input, and vector data on the q output is the result.