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- 15.3.12. Fully-Parallel FFTs with Flexible Ordering (FFT2X, FFT4X, FFT8X, FFT16X, FFT32X, and FFT64X)
- 15.3.13. General Multitwiddle and General Twiddle (GeneralMultiTwiddle, GeneralMultVTwiddle, GeneralTwiddle, GeneralVTwiddle)
7.8.7. Primitive Systolic FIR with Forward Flow Control
The top-level testbench includes Control and Signals blocks.
The FirChip subsystem includes the Device block and a lower-level Primitive FIR subsystem.
The Primitive FIR subsystem includes ChannelIn, ChannelOut, Mux, SampleDelay, Const, Mult, Add, and SynthesisInfo blocks.
In this design example, the top level of the FPGA device (marked by the Device block) and the synthesizable primitive FIR subsystem (marked by the SynthesisInfo block) are at different hierarchy levels.
The design example has a sequence of three FIR filters that stall when the valid signal is low, preventing invalid data polluting the datapath. The design example has a regular filter structure, but with a delay line implemented in single-cycle latches—effectively an enabled delay line.
You need not enable everything in the filter (multipliers, adders, and so on), just the blocks with state (the registers). Then observe the output valid signal, which DSP Builder pipelines with the logic, and observe the valid output data only.
You can also use vectors to implement the constant multipliers and adder tree, which also speeds up simulation. You can improve the design example further with the TappedDelayLine block.
The model file is demo_forward_pressure.mdl.
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