DSP Builder for Intel® FPGAs (Advanced Blockset): Handbook

ID 683337
Date 6/20/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

4.7.3.3. Updating Registers with the Nios II Processor

You can use a processor such as a Nios II processor to read or modify a control register, or to update memory contents in your DSP Builder design.

Procedure

  1. Identify the Platform Designer base address assigned to your DSP Builder design. You can also find the base address information in system.h file in your Nios II project, after you have loaded the SOPC library information into your Nios II IDE.
  2. Identify the base address for the IP block of interest in your DSP Builder advanced blockset design. It is the base address assigned to your DSP Builder advanced blockset model for step 1, plus the address offset you specified in your IP block or in your setup script. You can also identify the address offset by right clicking on the IP block and selecting Help.
  3. Identify the base address for the register of interest in your DSP Builder advanced blockset design. It is the base address assigned to your DSP Builder advanced blockset model which you identify in step 1, plus the address offset you specified in your register or in your setup script.
    1. Identify the address offset in the <design name> _mmap.h file, which DSP Builder generates with each design.
    2. Alternatively, identify the address offset by right clicking on the register and select Help.
  4. When you identify the base address, use IOWR and IORD commands to write and read registers and memory. For example:
    IOWR(base_addr_SOPC + base_addr_FIR, coef_x_offset, data)
    IORD(base_addr_SOPC + base_addr_FIR, coef_x_offset)