1.3.1. Create detailed design specifications 1.3.2. Create detailed functional verification or test plan 1.3.3. Select IP that affects system design, especially I/O interfaces 1.3.4. Ensure your board design supports the Intel® FPGA IP Evaluation Mode tethered mode 1.3.5. Review available system development tools
1.4.1. Consider the available device variants 1.4.2. Estimate the required logic, memory, and multiplier density 1.4.3. Consider vertical device migration availability and requirements 1.4.4. Review resource utilization reports of similar designs 1.4.5. Reserve device resources for future development and debugging 1.4.6. Estimate the number of I/O pins that you require 1.4.7. Consider the I/O pins you need to reserve for debugging 1.4.8. Verify that the number of LVDS channels are enough 1.4.9. Verify the number of PLLs and clock routing resources 1.4.10. Determine the device speed grade that you require 1.4.11. Determine the number of images supported for the device
126.96.36.199. Select a configuration scheme 188.8.131.52. Ensure board support the required features: 184.108.40.206. Plan for the Auto-restart after configuration error option 220.127.116.11. Estimating configuration file size 18.104.22.168. Review available on-chip debugging tools 22.214.171.124. Consider the guidelines to plan for debugging tools 126.96.36.199. Use the Early Power Estimator (EPE) to estimate power supplies and cooling solution
188.8.131.52. Design the board for power-up 184.108.40.206. Review the list of required supply voltages and the power supply options 220.127.116.11. Ensure I/O power pin compatibility with I/O standards 18.104.22.168. Ensure correct power pin connections 22.214.171.124. Determine power rail sharing 126.96.36.199. Use power distribution network (PDN) tool to plan for power distribution and decoupling capacitor selection 188.8.131.52. Review the following guidelines for PLL board design
184.108.40.206. Verify configuration pin connections and pull-up or pull-down resistors are correct for your configuration schemes 220.127.116.11. Design configuration TCK pin using the same technique as in designing high-speed signal or system clock 18.104.22.168. Verify the JTAG pins are connected to a stable voltage level if not in use 22.214.171.124. Verify the JTAG pin connections to the download cable header 126.96.36.199. Review the following JTAG pin connections guidelines: 188.8.131.52. Ensure the download cable and JTAG pin voltages are compatible 184.108.40.206. Buffer the JTAG signal according to the following guidelines: 220.127.116.11. Ensure all devices in the chain are connected properly 18.104.22.168. Determine if you need to turn on device-wide output enable
22.214.171.124. Specify the state of unused I/O pins 126.96.36.199. Refer to the Board Design Resource Center 188.8.131.52. Design VREF pins to be noise free 184.108.40.206. Refer to the Board Design Guideline Solution Center 220.127.116.11. Verify I/O termination and impedance matching 18.104.22.168. Perform full board routing simulation using IBIS models 22.214.171.124. Configure board trace models for Intel® Quartus® Prime advanced timing analysis 126.96.36.199. Review your pin connections
188.8.131.52. Determine if your system requires single-ended I/O signaling 184.108.40.206. Determine if your system requires voltage-referenced signaling 220.127.116.11. Determine if your system requires differential signaling 18.104.22.168. Select a suitable signaling type and I/O standard for each I/O pin 22.214.171.124. Verify that all output signals in each I/O bank are intended to drive out at the bank's assigned VCCIO voltage level 126.96.36.199. Verify that all voltage-referenced signals in each I/O bank are intended to use the bank's VREF voltage (for devices that support VREF pins) 188.8.131.52. Check the I/O bank support for LVDS features 184.108.40.206. Verify the usage of the VREF pins that are used as regular I/Os 220.127.116.11. Test pin connections with boundary-scan test 18.104.22.168. Use the UNIPHY IP core for each memory interface, and follow connection guidelines 22.214.171.124. Use dedicated DQ/DQS pins and DQ groups for memory interfaces 126.96.36.199. Make dual-purpose pin settings and check for any restrictions when using these pins as regular I/O 188.8.131.52. Review available device I/O features that can help I/O interfaces 184.108.40.206. Consider OCT features to save board space and verify that the required termination scheme is supported for all pin locations
220.127.116.11. Use the device PLLs for clock management 18.104.22.168. Ensure that you select the correct PLL feedback compensation mode 22.214.171.124. Check that the PLL offers the required number of clock outputs and use dedicated clock output pins 126.96.36.199. Use the clock control block for clock selection and power-down 188.8.131.52. Instantiate PLL with ADC
1.7.1. Use synchronous design practices 1.7.2. Consider the following recommendations to avoid clock signals problems: 1.7.3. Use IP cores with the parameter editor 1.7.4. Review the information on dynamic reconfiguration feature 1.7.5. Consider the Intel's recommended coding styles to achieve optimal synthesis results 1.7.6. Enable the chip-wide reset to clear all registers if required 1.7.7. Use device architecture-specific register control signals 1.7.8. Review recommended reset architecture 1.7.9. Review the synthesis options available in your synthesis tool 1.7.10. Consider resources available for register power-up and control signals 1.7.11. Consider Intel's recommendations for creating design partitions 1.7.12. Perform timing budgeting and resource balancing between partitions 1.7.13. Create a design floorplan for incremental compilation partitions
184.108.40.206. Specify your synthesis tool and use correct supported version 220.127.116.11. Review resource utilization reports after compilation 18.104.22.168. Review all Intel® Quartus® Prime messages, especially warning or error messages 22.214.171.124. Consider using incremental compilation 126.96.36.199. Ensure parallel compilation is enabled 188.8.131.52. Use the Compilation Time Advisor
184.108.40.206. Ensure timing constraints are complete and accurate 220.127.116.11. Review the Timing Analyzer reports after compilation 18.104.22.168. Ensure that the I/O timings are not violated when data is provided to the FPGA 22.214.171.124. Perform Early Timing Estimation before running a full compilation 126.96.36.199. Consider the following recommendations for timing optimization and analysis assignment: 188.8.131.52. Perform functional simulation at the beginning of your design flow 184.108.40.206. Perform timing simulation to ensure your design works in targeted device 220.127.116.11. Specify your simulation tool and use correct supported version
18.104.22.168. Provide accurate typical signal activities to get accurate power analysis result 22.214.171.124. Specify the correct operating conditions for power analysis 126.96.36.199. Analyze power consumption and heat dissipation in the Power Analyzer 188.8.131.52. Review recommended design techniques and Intel® Quartus® Prime options to optimize power consumption 184.108.40.206. Consider using a faster speed grade device 220.127.116.11. Optimize the clock power management 18.104.22.168. Reduce the number of memory clocking events 22.214.171.124. Consider I/O power guidelines 126.96.36.199. Reduce design glitches through pipelining and retiming 188.8.131.52. Review the information on power-driven compilation and Power Optimization Advisor 184.108.40.206. Reduce power consumption with architectural optimization
220.127.116.11. Consider the following recommendations to mitigate I/O simultaneous switching noise:
- Analyze the design for possible SSN problems.
- Reduce the number of pins that switch the voltage level at exactly the same time whenever possible.
- Use differential I/O standards and lower-voltage standards for high-switching I/Os.
- Use lower drive strengths for high-switching I/Os. The default drive strength setting might be higher than your design requires.
- Reduce the number of simultaneously switching output pins within each bank. Spread output pins across multiple banks if possible.
- Spread the switching I/Os evenly throughout the bank to reduce the number of aggressors in a given area to reduce SSN if bank usage is substantially below 100%.
- Separate simultaneously switching pins from input pins that are susceptible to SSN.
- Place important clock and asynchronous control signals near ground signals and away from large switching buses.
- Avoid using I/O pins one or two pins away from PLL power supply pins for high-switching or high-drive strength pins.
- Use staggered output delays to shift the output signals through time, or use adjustable slew rate settings.
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