Intel® MAX® 10 FPGA Design Guidelines

ID 683196
Date 10/19/2020
Document Table of Contents Consider the following recommendations to mitigate I/O simultaneous switching noise:

  • Analyze the design for possible SSN problems.
  • Reduce the number of pins that switch the voltage level at exactly the same time whenever possible.
  • Use differential I/O standards and lower-voltage standards for high-switching I/Os.
  • Use lower drive strengths for high-switching I/Os. The default drive strength setting might be higher than your design requires.
  • Reduce the number of simultaneously switching output pins within each bank. Spread output pins across multiple banks if possible.
  • Spread the switching I/Os evenly throughout the bank to reduce the number of aggressors in a given area to reduce SSN if bank usage is substantially below 100%.
  • Separate simultaneously switching pins from input pins that are susceptible to SSN.
  • Place important clock and asynchronous control signals near ground signals and away from large switching buses.
  • Avoid using I/O pins one or two pins away from PLL power supply pins for high-switching or high-drive strength pins.
  • Use staggered output delays to shift the output signals through time, or use adjustable slew rate settings.

Did you find the information on this page useful?

Characters remaining:

Feedback Message