1.3.1. Create detailed design specifications 1.3.2. Create detailed functional verification or test plan 1.3.3. Select IP that affects system design, especially I/O interfaces 1.3.4. Ensure your board design supports the Intel® FPGA IP Evaluation Mode tethered mode 1.3.5. Review available system development tools
1.4.1. Consider the available device variants 1.4.2. Estimate the required logic, memory, and multiplier density 1.4.3. Consider vertical device migration availability and requirements 1.4.4. Review resource utilization reports of similar designs 1.4.5. Reserve device resources for future development and debugging 1.4.6. Estimate the number of I/O pins that you require 1.4.7. Consider the I/O pins you need to reserve for debugging 1.4.8. Verify that the number of LVDS channels are enough 1.4.9. Verify the number of PLLs and clock routing resources 1.4.10. Determine the device speed grade that you require 1.4.11. Determine the number of images supported for the device
18.104.22.168. Select a configuration scheme 22.214.171.124. Ensure board support the required features: 126.96.36.199. Plan for the Auto-restart after configuration error option 188.8.131.52. Estimating configuration file size 184.108.40.206. Review available on-chip debugging tools 220.127.116.11. Consider the guidelines to plan for debugging tools 18.104.22.168. Use the Early Power Estimator (EPE) to estimate power supplies and cooling solution
22.214.171.124. Design the board for power-up 126.96.36.199. Review the list of required supply voltages and the power supply options 188.8.131.52. Ensure I/O power pin compatibility with I/O standards 184.108.40.206. Ensure correct power pin connections 220.127.116.11. Determine power rail sharing 18.104.22.168. Use power distribution network (PDN) tool to plan for power distribution and decoupling capacitor selection 22.214.171.124. Review the following guidelines for PLL board design
126.96.36.199. Verify configuration pin connections and pull-up or pull-down resistors are correct for your configuration schemes 188.8.131.52. Design configuration TCK pin using the same technique as in designing high-speed signal or system clock 184.108.40.206. Verify the JTAG pins are connected to a stable voltage level if not in use 220.127.116.11. Verify the JTAG pin connections to the download cable header 18.104.22.168. Review the following JTAG pin connections guidelines: 22.214.171.124. Ensure the download cable and JTAG pin voltages are compatible 126.96.36.199. Buffer the JTAG signal according to the following guidelines: 188.8.131.52. Ensure all devices in the chain are connected properly 184.108.40.206. Determine if you need to turn on device-wide output enable
220.127.116.11. Specify the state of unused I/O pins 18.104.22.168. Refer to the Board Design Resource Center 22.214.171.124. Design VREF pins to be noise free 126.96.36.199. Refer to the Board Design Guideline Solution Center 188.8.131.52. Verify I/O termination and impedance matching 184.108.40.206. Perform full board routing simulation using IBIS models 220.127.116.11. Configure board trace models for Intel® Quartus® Prime advanced timing analysis 18.104.22.168. Review your pin connections
22.214.171.124. Determine if your system requires single-ended I/O signaling 126.96.36.199. Determine if your system requires voltage-referenced signaling 188.8.131.52. Determine if your system requires differential signaling 184.108.40.206. Select a suitable signaling type and I/O standard for each I/O pin 220.127.116.11. Verify that all output signals in each I/O bank are intended to drive out at the bank's assigned VCCIO voltage level 18.104.22.168. Verify that all voltage-referenced signals in each I/O bank are intended to use the bank's VREF voltage (for devices that support VREF pins) 22.214.171.124. Check the I/O bank support for LVDS features 126.96.36.199. Verify the usage of the VREF pins that are used as regular I/Os 188.8.131.52. Test pin connections with boundary-scan test 184.108.40.206. Use the UNIPHY IP core for each memory interface, and follow connection guidelines 220.127.116.11. Use dedicated DQ/DQS pins and DQ groups for memory interfaces 18.104.22.168. Make dual-purpose pin settings and check for any restrictions when using these pins as regular I/O 22.214.171.124. Review available device I/O features that can help I/O interfaces 126.96.36.199. Consider OCT features to save board space and verify that the required termination scheme is supported for all pin locations
188.8.131.52. Use the device PLLs for clock management 184.108.40.206. Ensure that you select the correct PLL feedback compensation mode 220.127.116.11. Check that the PLL offers the required number of clock outputs and use dedicated clock output pins 18.104.22.168. Use the clock control block for clock selection and power-down 22.214.171.124. Instantiate PLL with ADC
1.7.1. Use synchronous design practices 1.7.2. Consider the following recommendations to avoid clock signals problems: 1.7.3. Use IP cores with the parameter editor 1.7.4. Review the information on dynamic reconfiguration feature 1.7.5. Consider the Intel's recommended coding styles to achieve optimal synthesis results 1.7.6. Enable the chip-wide reset to clear all registers if required 1.7.7. Use device architecture-specific register control signals 1.7.8. Review recommended reset architecture 1.7.9. Review the synthesis options available in your synthesis tool 1.7.10. Consider resources available for register power-up and control signals 1.7.11. Consider Intel's recommendations for creating design partitions 1.7.12. Perform timing budgeting and resource balancing between partitions 1.7.13. Create a design floorplan for incremental compilation partitions
126.96.36.199. Specify your synthesis tool and use correct supported version 188.8.131.52. Review resource utilization reports after compilation 184.108.40.206. Review all Intel® Quartus® Prime messages, especially warning or error messages 220.127.116.11. Consider using incremental compilation 18.104.22.168. Ensure parallel compilation is enabled 22.214.171.124. Use the Compilation Time Advisor
126.96.36.199. Ensure timing constraints are complete and accurate 188.8.131.52. Review the Timing Analyzer reports after compilation 184.108.40.206. Ensure that the I/O timings are not violated when data is provided to the FPGA 220.127.116.11. Perform Early Timing Estimation before running a full compilation 18.104.22.168. Consider the following recommendations for timing optimization and analysis assignment: 22.214.171.124. Perform functional simulation at the beginning of your design flow 126.96.36.199. Perform timing simulation to ensure your design works in targeted device 188.8.131.52. Specify your simulation tool and use correct supported version
184.108.40.206. Provide accurate typical signal activities to get accurate power analysis result 220.127.116.11. Specify the correct operating conditions for power analysis 18.104.22.168. Analyze power consumption and heat dissipation in the Power Analyzer 22.214.171.124. Review recommended design techniques and Intel® Quartus® Prime options to optimize power consumption 126.96.36.199. Consider using a faster speed grade device 188.8.131.52. Optimize the clock power management 184.108.40.206. Reduce the number of memory clocking events 220.127.116.11. Consider I/O power guidelines 18.104.22.168. Reduce design glitches through pipelining and retiming 22.214.171.124. Review the information on power-driven compilation and Power Optimization Advisor 126.96.36.199. Reduce power consumption with architectural optimization
1.7.13. Create a design floorplan for incremental compilation partitions
- A design floorplan avoids conflicts between design partitions and ensure that each partition is well-placed relative to other partitions. When you create different location assignments for each partition, no location conflicts occur.
- A design floorplan helps avoid situations in which the Fitter is directed to place or replace a portion of the design in an area of the device where most resources have already been claimed.
- Floorplan assignments are recommended for timing-critical partitions in top-down flows. You can use the Intel® Quartus® Prime Chip Planner to create a design floorplan using Logic Lock (Standard) region assignments for each design partition.
- With a basic design framework for the top-level design, the floorplan editor enables you to view connections between regions, estimate physical timing delays on the chip, and move regions around the device floorplan.
- After you compiled the full design, you can also view logic placement and locate areas of routing congestion to improve the floorplan assignments.
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