Intel® MAX® 10 FPGA Design Guidelines

ID 683196
Date 10/19/2020
Document Table of Contents

1.7.13. Create a design floorplan for incremental compilation partitions

  • A design floorplan avoids conflicts between design partitions and ensure that each partition is well-placed relative to other partitions. When you create different location assignments for each partition, no location conflicts occur.
  • A design floorplan helps avoid situations in which the Fitter is directed to place or replace a portion of the design in an area of the device where most resources have already been claimed.
  • Floorplan assignments are recommended for timing-critical partitions in top-down flows. You can use the Intel® Quartus® Prime Chip Planner to create a design floorplan using Logic Lock (Standard) region assignments for each design partition.
  • With a basic design framework for the top-level design, the floorplan editor enables you to view connections between regions, estimate physical timing delays on the chip, and move regions around the device floorplan.
  • After you compiled the full design, you can also view logic placement and locate areas of routing congestion to improve the floorplan assignments.

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