MAX® 10 FPGA Design Guidelines

ID 683196
Date 5/15/2024
Document Table of Contents Provide accurate typical signal activities to get accurate power analysis result

You need to provide accurate typical signal activities to Power Analyzer:
  • Compile a design to derive the information about design resources, placement and routing, and I/O standards.
  • Derive signal activity data (toggle rates and static probabilities) from simulation results or a user-defined default toggle rate and vectorless estimation. The signal activities used for analysis must be representative of the actual operating behavior.

    For the most accurate power estimation, use gate-level simulation results with a Value Change Dump File (.vcd) output file from a third-party simulation tool. The simulation activity should include typical input vectors over a realistic time period and not the corner cases often used during functional verification. Use the recommended simulator settings, such as glitch filtering, to ensure good results.