MAX® 10 FPGA Design Guidelines

ID 683196
Date 5/15/2024
Document Table of Contents Consider the following recommendations for timing optimization and analysis assignment:

  • Turn on Optimize multi-corner timing on the Fitter Settings page in the Settings dialog box.
  • Use create_clock and create_generated_clock to specify the frequencies and relationships for all clocks in your design.
  • Use set_input_delay and set_output_delay to specify the external device or board timing parameters
  • Use derive_pll_clocks to create generated clocks for all PLL outputs, according to the settings in the PLL IP cores. Specify multicycle relationships for LVDS transmitters or receiver deserialization factors.
  • Use derive_clock_uncertainty to automatically apply inter-clock, intra-clock, and I/O interface uncertainties.
  • Use check_timing to generate a report on any problem with the design or applied constraints, including missing constraints
  • Use the Quartus® Prime optimization features to achieve timing closure or improve the resource utilization.
  • Use the Timing and Area Optimization Advisors to suggest optimization settings.