MAX® 10 FPGA Design Guidelines

ID 683196
Date 5/15/2024
Document Table of Contents

1.9. Document Revision History for the MAX® 10 Device Design Guidelines

Document Version Changes
2024.05.15 Updated the guidelines for the download cable voltage in the Verify the JTAG pin connections to the download cable header section.
2020.10.19 Updated VREF pin support for voltage-referenced I/O standards in the Verify that all voltage-referenced signals in each I/O bank are intended to use the bank's VREF voltage (for devices that support VREF pins) section.
  • Updated the POR delay guideline in the Design the board for power-up section.
  • Updated the following terms:
    • Changed Qsys to Platform Designer (Standard).
    • Changed TimeQuest Timing Analyzer to Timing Analyzer.
    • Changed OpenCore Plus to Intel FPGA IP Evaluation Mode.
    • Changed PowerPlay Early Power Estimator to Early Power Estimator.
    • Changed LogicLock to Logic Lock (standard).
Date Version Changes
May 2017 2017.05.03
  • Rebranded as Intel.
December 2014 2014.12.15
  • Changed the following terms:

    Dual image to dual configuration image

    Dual image configuration to dual configuration

  • Changed MAX 10 EMIF IP core to UNIPHY IP core.
September 2014 2014.09.22 Initial release.