Intel® MAX® 10 FPGA Design Guidelines

ID 683196
Date 10/19/2020
Public
Document Table of Contents

1.8.4.8. Consider I/O power guidelines

  • The dynamic power consumed in the I/O buffer is proportional to the total load capacitance—lower capacitance reduces power consumption.
  • Dynamic power is proportional to the square of the voltage. Use lower voltage I/O standards to reduce dynamic power. Non-terminated I/O standards such as LVTTL and LVCMOS have a rail-to-rail output swing equal to the VCCIO supply voltage and consume little static power.
  • Dynamic power is proportional to the output transition frequency. Use resistively-terminated I/O standards such as SSTL for high-frequency applications. The output load voltage swings by an amount smaller than the VCCIO around a bias point. Because of this, the dynamic power is lower than for non-terminated I/O under similar conditions.
  • Resistively-terminated I/O standards dissipate significant static power because current is constantly driven into the termination network. Use the lowest drive strength that meets your speed and waveform requirements to minimize static power when using resistively terminated I/O standards.
  • The power used by external devices is not included in the Power Analyzer calculations. Ensure that you include the external devices power separately in your system power calculations.