MAX® 10 FPGA Design Guidelines

ID 683196
Date 5/15/2024
Document Table of Contents

1.7.2. Consider the following recommendations to avoid clock signals problems:

  • Use dedicated clock pins and clock routing for best results—dedicated clock pins drive the clock network directly, ensuring lower skew than other I/O pins. Use the dedicated routing network to have a predictable delay with less skew for high fan-out signals. You can also use the clock pins and clock network to drive control signals like asynchronous reset.
  • For clock inversion, multiplication, and division use the device PLLs.
  • For clock multiplexing and gating, use the dedicated clock control block or PLL clock switchover feature instead of combinational logic.
  • If you must use internally generated clock signals, register the output of any combinational logic used as a clock signal to reduce glitches. For example, if you divide a clock using combinational logic, clock the final stage with the clock signal that was used to clock the divider circuit.
  • In multi-clock designs, ensure that signals crossing clock domains are properly synchronized using the synchronizer, a handshake mechanism, or a FIFO.