Intel® MAX® 10 FPGA Design Guidelines

ID 683196
Date 10/19/2020
Document Table of Contents Specify the state of unused I/O pins

  • To reduce power dissipation, set clock pins and other unused I/O pins As inputs tri-stated. By default, the Intel® Quartus® Prime software set the input pins tri-stated with weak pull-up resistor enabled.
  • To improve signal integrity, in the Reserve all unused pins option under the Unused Pins category of the Device and Pin Options dialog box of the Intel® Quartus® Prime software, set the unused pins As output driving ground. This setting reduces inductance by creating a shorter return path and reduces noise on the neighboring I/Os. However, do not use this approach if it results in many via paths that causes congestion for signals under the device.
  • Carefully check the pin connections in the Pin-Out File (.pin) generated by the Intel® Quartus® Prime software when you compile your design. The .pin file specifies how you should connect the device pins. I/O pins specified as GND can be left unconnected or connected to ground for improved noise immunity. Do not connect RESERVED pins.

Did you find the information on this page useful?

Characters remaining:

Feedback Message