Intel® MAX® 10 FPGA Design Guidelines

ID 683196
Date 10/19/2020
Document Table of Contents Use the UNIPHY IP core for each memory interface, and follow connection guidelines

The self-calibrating UNIPHY IP core is optimized to take advantage of the Intel® MAX® 10 structure. The UNIPHY IP core allows you to set external memory interface features and helps set up the physical interface (PHY) best suited for your system. When you use the Intel® memory controller IP core functions, the UNIPHY IP core is instantiated automatically.

If you design multiple memory interfaces into the device using Intel® FPGA IP, generate a unique interface for each instance to ensure good results instead of designing it once and instantiating it multiple times.

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