MAX® 10 FPGA Design Guidelines

ID 683196
Date 5/15/2024
Document Table of Contents Refer to the Board Design Guideline Solution Center

Noise generated by SSN—when too many pins in close proximity change voltage levels at the same time—can reduce the noise margin and cause incorrect switching. For example, consider these board layout recommendations:
  • Break out large bus signals on board layers close to the device to reduce cross talk.
  • If possible, route traces orthogonally if two signal layers are next to each other, and use a separation of two to three times the trace width.