Intel® MAX® 10 FPGA Design Guidelines

ID 683196
Date 10/19/2020
Public
Document Table of Contents

1.6.1.3. Check I/O restrictions related to ADC usage

The Intel® Quartus® Prime software uses physics-based rules to define the number of I/O pins allowed in a particular bank based on the I/O's drive strength. These rules are based on noise calculation to analyze accurately the impact of I/O placement on the ADC performance. If you use the ADC block in your design, Intel recommends that you follow the guidelines.