Intel® MAX® 10 FPGA Design Guidelines

ID 683196
Date 10/19/2020
Document Table of Contents Use the Intel® Quartus® Prime Pin Planner for I/O pin planning, assignments, and validation

Early in the design process, the system architect typically has information about the standard I/O interfaces (such as memory and bus interfaces), IP cores to be used in the design, and any other I/O-related assignments defined by system requirements.

You can use the Intel® Quartus® Prime Pin Planner for I/O pin assignment planning, assignment, and validation:

  • The Intel® Quartus® Prime Start I/O Assignment Analysis command checks that pin locations and assignments are supported in the target FPGA architecture. Checks include reference voltage pin usage, pin location assignments, and mixing of I/O standards.
  • You can use I/O Assignment Analysis to validate I/O-related assignments that you make or modify throughout the design process.
  • The Create/Import IP core feature of the Pin Planner interfaces with the parameter editor, and enables you to create or import custom IP cores that use I/O interfaces.
  • Enter PLL and LVDS blocks. Then, use the Create Top-Level Design File command to generate a top-level design netlist file.
  • You can use the I/O analysis results to change pin assignments or IP parameters and repeat the checking process until the I/O interface meets your design requirements and passes the pin checks in the Intel® Quartus® Prime software.

    After planning is complete, you can pass the preliminary pin location information to PCB designers.

    After the design is complete, you can use the reports and messages generated by the Intel® Quartus® Prime Fitter for the final sign-off of the pin assignments.

Did you find the information on this page useful?

Characters remaining:

Feedback Message