MAX® 10 FPGA Design Guidelines

ID 683196
Date 5/15/2024
Document Table of Contents Design configuration TCK pin using the same technique as in designing high-speed signal or system clock

  • Noise on the TCK signal can affect JTAG configuration.
  • For a chain of devices, noise on the TCK pin in the chain can cause JTAG programming or configuration to fail for the entire chain.
  • For a chain of devices, ensure all devices in the JTAG chain are powered on during JTAG programming or configuration.