1.3.1. Create detailed design specifications 1.3.2. Create detailed functional verification or test plan 1.3.3. Select IP that affects system design, especially I/O interfaces 1.3.4. Ensure your board design supports the Intel® FPGA IP Evaluation Mode tethered mode 1.3.5. Review available system development tools
1.4.1. Consider the available device variants 1.4.2. Estimate the required logic, memory, and multiplier density 1.4.3. Consider vertical device migration availability and requirements 1.4.4. Review resource utilization reports of similar designs 1.4.5. Reserve device resources for future development and debugging 1.4.6. Estimate the number of I/O pins that you require 1.4.7. Consider the I/O pins you need to reserve for debugging 1.4.8. Verify that the number of LVDS channels are enough 1.4.9. Verify the number of PLLs and clock routing resources 1.4.10. Determine the device speed grade that you require 1.4.11. Determine the number of images supported for the device
188.8.131.52. Select a configuration scheme 184.108.40.206. Ensure board support the required features: 220.127.116.11. Plan for the Auto-restart after configuration error option 18.104.22.168. Estimating configuration file size 22.214.171.124. Review available on-chip debugging tools 126.96.36.199. Consider the guidelines to plan for debugging tools 188.8.131.52. Use the Early Power Estimator (EPE) to estimate power supplies and cooling solution
184.108.40.206. Design the board for power-up 220.127.116.11. Review the list of required supply voltages and the power supply options 18.104.22.168. Ensure I/O power pin compatibility with I/O standards 22.214.171.124. Ensure correct power pin connections 126.96.36.199. Determine power rail sharing 188.8.131.52. Use power distribution network (PDN) tool to plan for power distribution and decoupling capacitor selection 184.108.40.206. Review the following guidelines for PLL board design
220.127.116.11. Verify configuration pin connections and pull-up or pull-down resistors are correct for your configuration schemes 18.104.22.168. Design configuration TCK pin using the same technique as in designing high-speed signal or system clock 22.214.171.124. Verify the JTAG pins are connected to a stable voltage level if not in use 126.96.36.199. Verify the JTAG pin connections to the download cable header 188.8.131.52. Review the following JTAG pin connections guidelines: 184.108.40.206. Ensure the download cable and JTAG pin voltages are compatible 220.127.116.11. Buffer the JTAG signal according to the following guidelines: 18.104.22.168. Ensure all devices in the chain are connected properly 22.214.171.124. Determine if you need to turn on device-wide output enable
126.96.36.199. Specify the state of unused I/O pins 188.8.131.52. Refer to the Board Design Resource Center 184.108.40.206. Design VREF pins to be noise free 220.127.116.11. Refer to the Board Design Guideline Solution Center 18.104.22.168. Verify I/O termination and impedance matching 22.214.171.124. Perform full board routing simulation using IBIS models 126.96.36.199. Configure board trace models for Intel® Quartus® Prime advanced timing analysis 188.8.131.52. Review your pin connections
184.108.40.206. Determine if your system requires single-ended I/O signaling 220.127.116.11. Determine if your system requires voltage-referenced signaling 18.104.22.168. Determine if your system requires differential signaling 22.214.171.124. Select a suitable signaling type and I/O standard for each I/O pin 126.96.36.199. Verify that all output signals in each I/O bank are intended to drive out at the bank's assigned VCCIO voltage level 188.8.131.52. Verify that all voltage-referenced signals in each I/O bank are intended to use the bank's VREF voltage (for devices that support VREF pins) 184.108.40.206. Check the I/O bank support for LVDS features 220.127.116.11. Verify the usage of the VREF pins that are used as regular I/Os 18.104.22.168. Test pin connections with boundary-scan test 22.214.171.124. Use the UNIPHY IP core for each memory interface, and follow connection guidelines 126.96.36.199. Use dedicated DQ/DQS pins and DQ groups for memory interfaces 188.8.131.52. Make dual-purpose pin settings and check for any restrictions when using these pins as regular I/O 184.108.40.206. Review available device I/O features that can help I/O interfaces 220.127.116.11. Consider OCT features to save board space and verify that the required termination scheme is supported for all pin locations
18.104.22.168. Use the device PLLs for clock management 22.214.171.124. Ensure that you select the correct PLL feedback compensation mode 126.96.36.199. Check that the PLL offers the required number of clock outputs and use dedicated clock output pins 188.8.131.52. Use the clock control block for clock selection and power-down 184.108.40.206. Instantiate PLL with ADC
1.7.1. Use synchronous design practices 1.7.2. Consider the following recommendations to avoid clock signals problems: 1.7.3. Use IP cores with the parameter editor 1.7.4. Review the information on dynamic reconfiguration feature 1.7.5. Consider the Intel's recommended coding styles to achieve optimal synthesis results 1.7.6. Enable the chip-wide reset to clear all registers if required 1.7.7. Use device architecture-specific register control signals 1.7.8. Review recommended reset architecture 1.7.9. Review the synthesis options available in your synthesis tool 1.7.10. Consider resources available for register power-up and control signals 1.7.11. Consider Intel's recommendations for creating design partitions 1.7.12. Perform timing budgeting and resource balancing between partitions 1.7.13. Create a design floorplan for incremental compilation partitions
220.127.116.11. Specify your synthesis tool and use correct supported version 18.104.22.168. Review resource utilization reports after compilation 22.214.171.124. Review all Intel® Quartus® Prime messages, especially warning or error messages 126.96.36.199. Consider using incremental compilation 188.8.131.52. Ensure parallel compilation is enabled 184.108.40.206. Use the Compilation Time Advisor
220.127.116.11. Ensure timing constraints are complete and accurate 18.104.22.168. Review the Timing Analyzer reports after compilation 22.214.171.124. Ensure that the I/O timings are not violated when data is provided to the FPGA 126.96.36.199. Perform Early Timing Estimation before running a full compilation 188.8.131.52. Consider the following recommendations for timing optimization and analysis assignment: 184.108.40.206. Perform functional simulation at the beginning of your design flow 220.127.116.11. Perform timing simulation to ensure your design works in targeted device 18.104.22.168. Specify your simulation tool and use correct supported version
22.214.171.124. Provide accurate typical signal activities to get accurate power analysis result 126.96.36.199. Specify the correct operating conditions for power analysis 188.8.131.52. Analyze power consumption and heat dissipation in the Power Analyzer 184.108.40.206. Review recommended design techniques and Intel® Quartus® Prime options to optimize power consumption 220.127.116.11. Consider using a faster speed grade device 18.104.22.168. Optimize the clock power management 22.214.171.124. Reduce the number of memory clocking events 126.96.36.199. Consider I/O power guidelines 188.8.131.52. Reduce design glitches through pipelining and retiming 184.108.40.206. Review the information on power-driven compilation and Power Optimization Advisor 220.127.116.11. Reduce power consumption with architectural optimization
18.104.22.168. Review your pin connections
Intel provides schematic review worksheets based on the device Pin Connection Guidelines and other board-level pin connections literature that you need to consider when you finalize your schematics.
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