Intel® MAX® 10 FPGA Design Guidelines

ID 683196
Date 10/19/2020
Public
Document Table of Contents

1.4.9. Verify the number of PLLs and clock routing resources

Verify that your chosen device density package combination includes enough PLLs and clock routing resources for your design. GCLK resources are shared between certain PLLs, which can affect the inputs that are available for use.