MAX® 10 FPGA Design Guidelines

ID 683196
Date 5/15/2024
Document Table of Contents Use the device PLLs for clock management

Connect clock inputs to specific PLLs to drive specific low-skew routing networks. Analyze the global resource availability for each PLL and the PLL availability for each clock input pin. Use the following descriptions for the clock signals in your design:
  • The GCLK networks can drive throughout the entire device, serving as low-skew clock sources for device logic.
  • IOEs and internal logic can also drive GCLKs to create internally generated GCLKs and other high fan-out control signals; for example, synchronous or asynchronous clears and clock enables.
  • PLLs cannot be driven by internally-generated GCLKs. The input clock to the PLL must come from dedicated clock input pins or from another pin/PLL-fed GCLK.