MAX® 10 FPGA Design Guidelines

ID 683196
Date 5/15/2024
Document Table of Contents Buffer the JTAG signal according to the following guidelines:

  • If a cable drives three or more devices, buffer the JTAG signal at the cable connector to prevent signal deterioration.
  • Anything added to the board that affects the inductance or capacitance of the JTAG signals increases the likelihood that a buffer should be added to the chain.
  • Each buffer should drive no more than eight loads for the TCK and TMS signals, which drive in parallel. If jumpers or switches are added to the path, decrease the number of loads.