Intel® MAX® 10 FPGA Design Guidelines

ID 683196
Date 10/19/2020
Document Table of Contents

1.7.1. Use synchronous design practices

In a synchronous design, a clock signal triggers all events. When all of the registers’ timing requirements are met, a synchronous design behaves in a predictable and reliable manner for all process, voltage, and temperature (PVT) conditions. You can easily target synchronous designs to different device families or speed grades.

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