MAX® 10 FPGA Design Guidelines

ID 683196
Date 5/15/2024
Document Table of Contents

1.7.12. Perform timing budgeting and resource balancing between partitions

If your design is created in multiple projects, it is important that the system architect provide guidance to designers of lower-level blocks to ensure that each partition uses the appropriate device resources:
  • Because the designs are developed independently, each lower-level designer has no information about the overall design or how their partition connects with other partitions, which can lead to problems during system integration.
  • The top-level project information, including pin locations, physical constraints, and timing requirements, should be communicated to the designers of lower-level partitions before they start their design.
  • The system architect can plan design partitions at the top level and use the Quartus® Prime software Generate Bottom-Up Design Partition Scripts option on the Project menu to automate the process of transferring top-level project information to lower-level modules.