Intel® SoC FPGA Embedded Development Suite (SoC EDS) User Guide

ID 683187
Date 3/12/2021
Document Table of Contents

7.3. System Memory Map

The addresses of the HPS hard IP modules are accessible through the provided SoCAL macros. SoCAL also provides macros for accessing the individual registers and register fields of the HPS hard IP modules.

For the FPGA IP modules, the macros for accessing IP registers and register fields are usually part of the IP deliverables. However, the actual IP modules-based addresses are often changed at system integration time, in the Platform Designer (Standard) tool.

The tool "sopc-create-header-files" can be used to create a C include file with the bases addresses of all the IP modules residing in the FPGA fabric.
Note: The tool is part of Intel® Quartus® Prime Standard Edition, and not of Intel® SoC FPGA EDS. The tool can be invoked from the SoC EDS Embedded Command Shell once Intel® Quartus® Prime Standard Edition is installed.

The basic usage of the tool is to invoke it with the .sopcinfo file as a single parameter. For example, in order to generate the include files for the Intel® Arria® 10 SoC GHRD, the following command can be executed in that folder: sopc-create-header-files ghrd_10as066n2.sopcinfo.

The tool creates a separate include file for each of the masters in the system, showing the system addresses from that master's point of view. Use the file <hps_component_name>_a9_0.h for HPS software development, as it shows the system addresses from the HPS point of view.

The following example demonstrates how to use the tool to generate only the file that shows the HPS A9 Core 0 point of view:
sopc-create-header-files ghrd_10as066n2.sopcinfo --module\ 
arria10_hps_0_arm_a9_0 --single arria10_hps_0_arm_a9_0.h 

This creates just one file, called "arria10_hps_0_arm_a9_0.h".

You can also run "sopc-create-header-files --help" for more details about the tool, or refer to Intel® Quartus® Prime Standard Edition documentation.