Intel® SoC FPGA Embedded Development Suite (SoC EDS) User Guide

ID 683187
Date 3/12/2021
Document Table of Contents Intel® Arria® 10 SoC Flow

For Intel® Arria® 10 SoC, you run the BSP Generator first, and it creates a Device Tree with default settings based on the Intel® Quartus® Prime handoff information. There is no source code generated, because all customization is encapsulated in the Bootloader Device Tree.
Note: The device tree is board specific and may need to be edited to reflect customer designs

The next step is to clone the U-Boot source code from GitHub, and copy the generated device tree into U-Boot source code. For complete instructions, go to the Building Bootloader web page on Then the U-Boot is compiled using the make utility and it creates the combined bootloader image, which contains both the bootloader executable and the bootloader device tree. You can download the combined image to a Flash device or FPGA RAM to use for booting the HPS.

Figure 21.  Intel® Arria® 10 SoC BSP Generator Flow

The hardware handoff information contains various settings that you entered when creating the hardware design in Platform Designer.. These include the following:

  • Pin-muxing for the HPS dedicated pins
  • I/O settings for the HPS dedicated pins:
    • Voltage
    • Slew rate
    • Pull up/ down
  • Pin-muxing for the shared pins
  • Configuration of the bridges between HPS and FPGA
  • Clock tree settings:
    • PLL settings
    • Clock divider settings
    • Clock gating settings

The handoff settings are output from the Intel® Quartus® Prime Standard Edition compilation and are located in the <quartus project directory>/hps_isw_handoff directory.

The user must run the BSP Generator and re-generate the Bootloader device tree each time a hardware change results in a change of the above parameters.

However, you does not have to always recompile the Bootloader whenever a hardware setting is changed. The Bootloader needs to be recompiled only when changing the boot source.