The boot flow for all the Intel SoC devices includes a bootloader. The bootloader has two stages called First Stage Bootloader (FSBL) and Second Stage Bootloader (SSBL). The FSBL is also known as Preloader.
The FSBL needs to fit into the on-chip RAM (OCRAM) and has limited functionality. It performs the tasks of initializing the HPS, bringing up the DDRAM and then loading and executing the next stage in the boot process. The next stage can be the SSBL, the end application, or an Operating System (OS).
The SSBL resides in DDRAM and therefore can have a larger size. Besides the ability to load and execute the next stage in the booting process, it typically offers a lot more functionality such as filesystem support, networking services, and command line interface.
On Cyclone® V SoC, Arria® V SoC and Intel® Arria® 10 SoC devices, the very first code run by HPS is the BootROM. For Intel® Stratix® 10 SoC and Intel® Agilex™ devices, the very first code run by HPS is the FSBL which is loaded by Secure Device Manager (SDM).
This chapter presents the tools that are used to enable the bootloader management:
- BSP Generator – enables you to get the Intel® Quartus® Prime handoff information and use it for the initial configuration of the bootloader for Cyclone® V SoC, Arria® V SoC and Intel® Arria® 10 SoC devices.
- Bootloader Image Tool ( mkpimage ) — enables you to add the BootROM-required header on top of the bootloader for Cyclone® V SoC, Arria® V SoC and Intel® Arria® 10 SoC devices.
- U-Boot Image Tool ( mkimage )— enables you to add the bootloader-required header on top of the files loaded by bootloader.
This chapter also includes instructions on how to build the bootloader for Intel® Stratix® 10 SoC and Intel® Agilex™ devices. For instructions on how to build the bootloader for Cyclone® V SoC, Arria® V SoC and Intel® Arria® 10 SoC, please visit "Building Bootloader" on RocketBoards.org.