Intel® SoC FPGA Embedded Development Suite (SoC EDS) User Guide

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ID 683187
Date 3/12/2021
Public
Document Table of Contents
Document Table of Contents
1. Introduction to the Intel® SoC FPGA Embedded Development Suite (SoC EDS) 2. Installing the Tools 3. Running the Tools 4. SoC EDS Licensing 5. Arm* Development Studio* for Intel® SoC FPGA Edition 6. Boot Tools User Guide 7. Hardware Library 8. Using the HPS Flash Programmer 9. Bare Metal Compilers 10. SD Card Boot Utility 11. Linux* Device Tree Generator 12. Support and Feedback
1. Introduction to the Intel® SoC FPGA Embedded Development Suite (SoC EDS)
1.1. Notice 1.2. Tool Versions 1.3. Differences Between Standard and Professional Editions 1.4. Overview 1.5. Hardware and Software Development Roles 1.6. Hardware – Software Development Flow 1.7. Introduction to the Intel® SoC FPGA EDS Revision History
1.5. Hardware and Software Development Roles
1.5.1. Hardware Engineer 1.5.2. Bare Metal and RTOS Developer 1.5.3. Linux* Kernel and Driver Developer 1.5.4. Linux* Application Developer
2. Installing the Tools
2.1. Installation Folders 2.2. Linux 2.3. Windows 2.4. Installing the Intel® SoC FPGA EDS Document Revision History
2.2. Linux
2.2.1. Installing SoC EDS 2.2.2. Installing Arm* DS* 2.2.3. Installing Linaro* Bare Metal Toolchain
2.3. Windows
2.3.1. Installing SoC EDS 2.3.2. Installing Arm* DS* 2.3.3. Installing Cygwin 2.3.4. Installing MinGW 2.3.5. Installing Linaro* Bare Metal Toolchain
3. Running the Tools
3.1. Linux* 3.2. Windows* 3.3. Running the Tools Revision History
4. SoC EDS Licensing
4.1. Getting the License 4.2. Activating the License 4.3. Intel® SoC FPGA EDS Licensing Revision History
5. Arm* Development Studio* for Intel® SoC FPGA Edition
5.1. Arm* DS* for Intel® SoC FPGA Edition Revision History
6. Boot Tools User Guide
6.1. Introduction 6.2. BSP Generator 6.3. Bootloader Image Tool (mkpimage) 6.4. U-Boot Image Tool (mkimage) 6.5. Building the Bootloader 6.6. Boot Tools User Guide Revision History
6.2. BSP Generator
6.2.1. BSP Generation Flow 6.2.2. BSP Generator Graphical User Interface 6.2.3. BSP Generator Command Line Interface 6.2.4. BSP Files and Folders 6.2.5. BSP Settings
6.2.1. BSP Generation Flow
6.2.1.1. Cyclone® V SoC and Arria® V SoC Flow 6.2.1.2. Intel® Arria® 10 SoC Flow
6.2.3. BSP Generator Command Line Interface
6.2.3.1. bsp-create-settings
6.3. Bootloader Image Tool (mkpimage)
6.3.1. Operation 6.3.2. Header File Format 6.3.3. Tool Usage 6.3.4. Output Image Layout
6.3.4. Output Image Layout
6.3.4.1. Base Address 6.3.4.2. Size 6.3.4.3. Address Alignment 6.3.4.4. Padding
6.3.4.3. Address Alignment
6.3.4.3.1. NAND Flash 6.3.4.3.2. Serial NOR Flash 6.3.4.3.3. SD/MMC
6.4. U-Boot Image Tool (mkimage)
6.4.1. Tool Options 6.4.2. Usage Examples
6.5. Building the Bootloader
6.5.1. Building the Cyclone® V SoC and Arria® V SoC Preloader 6.5.2. Building the Intel® Arria® 10 SoC Bootloader 6.5.3. Building the Intel® Stratix® 10 SoC and Intel® Agilex™ Devices
7. Hardware Library
7.1. Feature Description 7.2. Hardware Library Reference Documentation 7.3. System Memory Map 7.4. Hardware Library Revision History
7.1. Feature Description
7.1.1. SoC Abstraction Layer (SoCAL) 7.1.2. HW Manager
8. Using the HPS Flash Programmer
8.1. HPS Flash Programmer Command-Line Utility 8.2. How the HPS Flash Programmer Works 8.3. Using the Flash Programmer from the Command Line 8.4. Supported Memory Devices 8.5. HPS Flash Programmer User Guide Revision History
8.3. Using the Flash Programmer from the Command Line
8.3.1. HPS Flash Programmer 8.3.2. HPS Flash Programmer Command Line Examples
9. Bare Metal Compilers
9.1. Arm* Bare Metal Compilers 9.2. Linaro* GCC Compiler 9.3. Bare Metal Compilers Revision History
10. SD Card Boot Utility
10.1. Usage Scenarios 10.2. Tool Options 10.3. SD Card Boot Utility Revision History
11. Linux* Device Tree Generator
11.1. Linux* Device Tree Generator Revision History
12. Support and Feedback
12.1. Support and Feedback Revision History
1. Introduction to the Intel® SoC FPGA Embedded Development Suite (SoC EDS)
2. Installing the Tools
3. Running the Tools
4. SoC EDS Licensing
5. Arm* Development Studio* for Intel® SoC FPGA Edition
6. Boot Tools User Guide
7. Hardware Library
8. Using the HPS Flash Programmer
9. Bare Metal Compilers
10. SD Card Boot Utility
11. Linux* Device Tree Generator
12. Support and Feedback

1.7. Introduction to the Intel® SoC FPGA EDS Revision History

Document Version Changes
2021.03.12 Added a Notice about where to receive up-to-date information about SoC EDS in the Introduction to the Intel® SoC FPGA EDS
2020.08.07 Added support for Intel® Quartus® Prime Standard Edition and Intel® Quartus® Prime Pro Edition software version 20.1 releases:
  • Replaced Mentor Graphics* Bare Metal GCC Compiler with Linaro* Bare Metal Compiler (GCC)
  • Updated the tool versions
  • Removed Linux* Compiler
  • Updated to Arm* Development Studio* (DS*) for Intel® SoC FPGA Edition
2019.12.20 Added support for Intel® Quartus® Prime Standard Edition version 19.1 and Intel® Quartus® Prime Pro Edition version 19.3
  • Added Intel® Agilex™ support.
  • Removed references to SoCEDSGettingStarted wiki.
  • Updated tool versions,
  • Removed the following chapters from the Introduction to the Intel® SoC FPGA Embedded Development Suite :
    • Linux Device Tree Binary
    • Intel® Stratix® 10 SoC Golden Hardware Reference Design
    • Removed the Getting Started Guides section from the document.
  • Linux Kernel and Driver Developer section: Added a link to HOWTOCreateADeviceTree on the Rocketboards.org website.
2019.05.16
  • Tool Versions section: Updated the Arm* Development Studio* (DS*) for Intel® SoC FPGA Edition version.
  • Intel® Stratix® 10 SoC SoC Golden Hardware Reference Design section: Updated the SoC EDS Professional Edition and Intel® Quartus® Prime Pro Edition versions.
2018.09.24 Updated the Tool versions for Arm* Compiler 6 and Arm* Development Studio* (DS*) for Intel® SoC FPGA Edition
2018.06.18
  • Updated chapter to include support for Intel® Stratix® 10 SoC
  • Replaced "Second Stage Bootloader" with "Bootloader".
  • For the Golden Hardware Reference Designs (GHRD), added the precompiled bootloader for Intel® Stratix® 10 SoC
  • Added the " Intel® Stratix® 10 SoC Golden Hardware Reference Design" section
2017.05.08
  • Intel FPGA rebranding
  • Rebranded paths and tools for the Standard and Professional versions
2016.11.07 Maintenance release
2016.05.27 Renamed the Web and Subscription Editions to align with Quartus Prime naming
2016.02.17 Maintenance release
2015.08.06 Added Intel® Arria® 10 SoC support
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