Intel® SoC FPGA Embedded Development Suite (SoC EDS) User Guide

ID 683187
Date 3/12/2021
Document Table of Contents
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1.6. Hardware – Software Development Flow

The Intel hardware-to-software handoff utilities allow hardware and software teams to work independently and follow their respective familiar design flows.

Figure 1.  Intel Hardware-to-Software Handoff

The following handoff files are created when the hardware project is compiled:

  • Handoff folder – contains information about how the HPS component is configured, including things like which peripherals are enabled, the pin MUXing and IOCSR settings, and memory parameters. The handoff folder is used by the second stage bootloader generator to create the preloader.

    For more information about the handoff folder, refer to the "BSP Generation Flow" section.

  • .svd file – contains descriptions of the HPS registers and of the soft IP registers on the FPGA side implemented in the FPGA portion of the device. The .svd file contains register descriptions for the HPS peripheral registers and soft IP components in the FPGA portion of the SoC. This file is used by the Arm* DS* for Intel® SoC FPGA Edition Debugger to allow you to inspect and modify these registers.
  • .sopcinfo file – contains a description of the entire system. The SOPC Information (.sopcinfo) file, containing a description of the entire system, is used by the Linux* device tree generator to create the device tree used by the Linux* kernel.
    For more information, refer to the "Linux* Device Tree Generator" section.
    Note: The soft IP register descriptions are not generated for all soft IP cores.
    Note: For Intel® Stratix® 10 SoC and Intel® Agilex™ SoC, the handoff information is part of the configuration bitstream, and the bootloader has direct access to it. Because of that there is no need for a Bootloader Generator tool in this case.