18.104.22.168. Cyclone® V SoC and Arria® V SoC Flow
For Cyclone® V SoC and Arria® V SoC, the BSP Generator is required to be run first, to convert some of the handoff files into C source code. After that, you need to clone the U-Boot source code from github. Then you use an U-Boot script called qts-filter to extract the information from the handoff folder, and the set of files created by the BSP Generator, and put them in the U-Boot source code folder. Then you use the U-Boot makefile to build the SPL image. The SPL image can then be downloaded to a Flash device or FPGA RAM to be used for booting HPS.
The hardware handoff information contains various settings that you entered when creating the hardware design in Platform Designer and Intel® Quartus® Prime Standard Edition. These include the following:
- Pin-muxing for the HPS dedicated pins
- I/O settings for the HPS dedicated pins:
- Slew rate
- Pull up/ down
- Configuration of the bridges between HPS and FPGA
- Clock tree settings:
- PLL settings
- Clock divider settings
- Clock gating settings
- DDR settings:
The handoff settings are output from the Intel® Quartus® Prime Standard Edition compilation and are located in the <quartus project directory>/hps_isw_handoff/<hps entity name> directory (where <hps entity name > is the HPS component name in Platform Designer).
You must update the hardware handoff files and regenerate the BSP each time a hardware change impacts the HPS, such as after pin multiplexing or pin assignment changes.
For complete instructions on how to build the bootloader for Cyclone® V SoC and Arria® V SoC, please visit "Building Bootloader" on RocketBoards.org.