Intel® SoC FPGA Embedded Development Suite (SoC EDS) User Guide
ID
683187
Date
2/03/2025
Public
1. Introduction to the SoC FPGA Embedded Development Suite (EDS)
2. Installing the Tools
3. Running the Tools
4. SoC FPGA EDS Licensing
5. Arm* Development Studio* for Intel® SoC FPGA Edition
6. Boot Tools User Guide
7. Hardware Library
8. Using the HPS Flash Programmer
9. Bare Metal Compilers
10. SD Card Boot Utility
11. Linux* Device Tree Generator
12. Support and Feedback
6.5.3. Building the Stratix® 10 SoC and Agilex™ 7 Devices
On Stratix® 10 SoC and Agilex™ 7 devices, the SDM loads the FSBL from the configuration bitstream. The configuration bitstream contains the hardware handoff data, which is made available to the FSBL. Because of this, there is no need for a Bootloader Generator tool to pass additional information to the Bootloader building process.
For information about how to build the Stratix® 10 SoC U-Boot, refer to the Building Bootloader webpage on RocketBoards.
For information about ATF and UEFI, refer to the Stratix® 10 SoC UEFI Boot Loader User Guide.
For information about the Stratix® 10 SoC bootloaders, refer to the Stratix® 10 SoC FPGA Boot User Guide.