Intel® SoC FPGA Embedded Development Suite User Guide

ID 683187
Date 8/07/2020
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Document Table of Contents

1.4.1. Hardware Engineer

As a hardware engineer, you typically design the FPGA hardware in Platform Designer. You can use the debugger of Arm* DS* for Intel® SoC FPGA Edition to connect to the Arm* cores and test the hardware. A convenient feature of the Arm* DS* for Intel® SoC FPGA Edition debugger is the soft IP register visibility, using Cortex Microcontroller Software Interface Standard (CMSIS) System View Description (.svd) files. With this feature, you can easily read and modify the soft IP registers from the Arm* side.

As a hardware engineer, you may generate the Preloader for your hardware configuration. The Preloader is a piece of software that configures the HPS component according to the hardware design.

As a hardware engineer, you may also perform the board bring-up. You can use Arm* DS* for Intel® SoC FPGA Edition debugger to verify that they can connect to the Arm and the board is working correctly.

These tasks require JTAG debugging, which is provided by the Arm* DS* for Intel® SoC FPGA Edition, which is provided through a separate download.

For more information, refer to the Installing the Intel® SoC FPGA EDS section.