188.8.131.52. Specifying a Power-Up Value
You can also specify the power-up level with an altera_attribute assignment in the source code. This attribute forces synthesis to perform NOT gate push-back, because synthesis tools cannot change the power-up states of core registers.
You can apply the Power-Up Level logic option to a specific register, or to a design entity, module, or sub design. When you assign this option, every register in that block receives the value. Registers power up to 0 by default. Therefore, you can use this assignment to force all registers to power-up to 1 using NOT gate push-back.
Setting the Power-Up Level to a logic level of high for a large design entity could degrade the quality of results due to the number of inverters that requires. In some situations, this design style causes issues due to enable signal inference or secondary control logic inference. It may also be more difficult to migrate this type of designs.
Some synthesis tools can also read the default or initial values for registered signals and implement this behavior in the device. For example, Intel® Quartus® Prime Pro Edition synthesis converts default values for registered signals into Power-Up Level settings. When the Intel® Quartus® Prime software reads the default values, the synthesized behavior matches the power-up state of the HDL code during a functional simulation.
Verilog Register with High Power-Up Value
reg q = 1’b1; //q has a default value of ‘1’ always @ (posedge clk) begin q <= d; end
VHDL Register with High Power-Up Level
SIGNAL q : STD_LOGIC := '1'; -- q has a default value of '1' PROCESS (clk, reset) BEGIN IF (rising_edge(clk)) THEN q <= d; END IF; END PROCESS;
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