3.4.6. Increase the Number of Stages Used in Synchronizers
If a synchronization chain is reported to have a low MTBF, consider adding an additional register stage to your synchronization chain. This additional stage increases the settling time of the synchronization chain, allowing more opportunity for the signal to resolve to a known state during a metastable event. Additional settling time increases the MTBF of the chain and improves the robustness of your design. However, adding a synchronization stage introduces an additional stage of latency on the signal.
If you use the Intel® FPGA IP core with separate read and write clocks to cross clock domains, increase the metastability protection (and latency) for better MTBF. In the DCFIFO parameter editor, choose the Best metastability protection, best fmax, unsynchronized clocks option to add three or more synchronization stages. You can increase the number of stages to more than three using the How many sync stages? setting.
Did you find the information on this page useful?