184.108.40.206. Register Combinational Logic Outputs
Narrow glitches can violate the register’s minimum pulse width requirements. Setup and hold requirements might also be violated if the data input of the register changes when a glitch reaches the clock input. Even if the design does not violate timing requirements, the register output can change value unexpectedly and cause functional hazards elsewhere in the design.
To avoid these problems, you should always register the output of combinational logic before you use it as a clock signal.
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