1.6.7. Comparator HDL Guidelines
Synthesis tools implement the == comparator in general logic cells and the < comparison in either the carry chain or general logic cells. In devices with 6-input ALUTs, the carry chain can compare up to three bits per cell. Carry chain implementation tends to be faster than general logic on standalone benchmark test cases, but can result in lower performance on larger designs due to increased restrictions on the Fitter. The area requirement is similar for most input patterns. The synthesis tools select an appropriate implementation based on the input pattern.
You can guide the Intel® Quartus® Prime Synthesis engine by choosing specific coding styles. To select a carry chain implementation explicitly, rephrase the comparison in terms of addition.
For example, the following coding style allows the synthesis tool to select the implementation, which is most likely using general logic cells in modern device families:
wire [6:0] a,b; wire alb = a<b;
wire [6:0] a,b; wire [7:0] tmp = a - b; wire alb = tmp
This second coding style uses the top bit of the tmp signal, which is 1 in two's complement logic if a is less than b, because the subtraction a - b results in a negative number.
If you have any information about the range of the input, you can use “don’t care” values to optimize the design. This information is not available to the synthesis tool, so specific hand implementation of the logic can reduce the device area required to implement the comparator.
The following logic structure, which occurs frequently in address decoders, allows you to check whether a bus value is within a constant range with a small amount of logic area:
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