Intel® Quartus® Prime Pro Edition User Guide: Design Recommendations

ID 683082
Date 8/03/2023
Document Table of Contents

3.1.1. Data Synchronization Register Chains

A synchronization register chain, or synchronizer, is defined as a sequence of registers that meets the following requirements:
  • The registers in the chain are all clocked by the same clock or phase-related clocks.
  • The first register in the chain is driven asynchronously or from an unrelated clock domain.
  • Each register fans out to only one register, except the last register in the chain.

For Intel® Quartus® Prime software to identify a synchronization register chain, the registers in the chain must not include any resets.

The length of the synchronization register chain is the number of registers in the synchronizing clock domain that meet the requirements listed earlier. The following figure shows a sample two-register synchronization chain.
Figure 46. Sample Synchronization Register Chain

The timing slack available in the register-to-register paths of the synchronizer allows a metastable signal to settle, and is referred to as the available settling time. The available settling time in the MTBF calculation for a synchronizer is the sum of the output timing slacks for each register in the chain. Adding available settling time with additional synchronization registers improves the metastability MTBF.