184.108.40.206.3. Priority Multiplexers
Synthesis tools commonly infer these structures from IF, ELSE, WHEN, SELECT, and ?: statements in VHDL or Verilog HDL.
VHDL IF Statement Implying Priority
The multiplexers form a chain, evaluating each condition or select bit sequentially.
IF cond1 THEN z <= a; ELSIF cond2 THEN z <= b; ELSIF cond3 THEN z <= c; ELSE z <= d; END IF;
Depending on the number of multiplexers in the chain, the timing delay through this chain can become large, especially for device families with 4-input LUTs.
To improve the timing delay through the multiplexer, avoid priority multiplexers if priority is not required. If the order of the choices is not important to the design, use a CASE statement to implement a binary or selector multiplexer instead of a priority multiplexer. If delay through the structure is important in a multiplexed design requiring priority, consider recoding the design to reduce the number of logic levels to minimize delay, especially along your critical paths.
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