- Updated the recommendation in Optimizing Clocking Schemes.
- Removed obsolete Block Based Design rule category from Design Assistant Design Rule Checking topic.
- Updated Design Assistant Design Rule Checking topic for latest rule categories.
- Updated Design Assistant Design Rule Checking topic with screenshot, minor wording changes, and link to AN 919: Improving Quality of Results with Design Assistant.
- Updated Setting Up Design Assistant topic for rule tags.
- Updated Running Design Assistant During Compilation step 4 wording.
- Updated Opening Design Assistant Rule Help topic to show rule included in this release.
- Updated screenshots in Cross-Probing from Design Assistant to Timing Analyzer topic.
- Removed Filtering and Hiding Rule Violations section as waivers are most effective method in current version.
- Updated Changing the Default Number of Violations per Rule for minor wording changes.
- Created new Design Assistant Tags topic to define all tags.
- Created new Design Assistant Waiver Dialog Box topic to define all settings in this dialog box. including new waiver features.
- Updated Creating Design Assistant Waivers topic for waiver preview and reporting.
- Updated Deleting Design Assistant Waivers topic for new GUI method.
- Updated Design Assistant Rule Categories topic for latest rule categories.
- Revised Design Assistant Rule Severity Levels descriptions.
- Added new "Waiving Design Assistant Rules" section.
- Added new "Cross-Probing with Design Assistant" section.
- Added description of new Fatal severity level Design Assistant rule to "Modifying Rule Severity Levels" topic.
- Updated "Setting Up Design Assistant" for new Fatal severity level and RDC rule category.
- Updated "Running Design Assistant in Analysis Mode" with screenshots and detailed steps.
- Added RDC to "Design Assistant Rule Categories" topic.
- Removed individual Design Assistant rule descriptions from document and linked to updated rule description in Help.
- Replaced obsolete rule screenshots throughout.
- Added support for Design Assistant during Timing Signoff to "Setting Up Design Assistant" and "Running Design Assistant During Compilation" topics.
- Added new Design Assistant rules.
- Revised Design Assistant rules HRR-10201, HRR-10201, and RES-30131.
- Removed various obsolete Design Assistant rules.
- Revised "Changing Design Assistant Rule Scope or Number of Violations" topic for clarity.
- Created separate "Clock Domain Crossing (CDC) Rules" category and topic.
- Added "CLK-30026: Missing Clock Assignment" Design Assistant rule.
- Added "CLK-30027: Multiple Clock Assignment" Design Assistant rule.
- Added "CLK-30028: Invalid Generated Clock" Design Assistant rule.
- Added "CLK-30029: Invalid Clock Assignment" Design Assistant rule.
- Added "CLK-30030: PLL Setting Violation" Design Assistant rule.
- Added "CLK-30031: Input Delay Assigned to Clock" Design Assistant rule.
- Added new "Setting Up Design Assistant" topic.
- Added new "Managing Design Assistant Rules" topic.
- Added new "Enabling Rules for Specific Compiler Stages" topic.
- Added new "Specifying Rule Parameters for Specific Compiler Stages" topic.
- Added new "Modifying Rule Severity Levels" topic.
- Added new "Filtering and Hiding Rule Violations" topic.
- Added new "Filter Options Dialog Box" topic.
- Added new "Linking to Design Assistant Rule Documentation" topic.
- Updated screenshots for latest GUI elements.
- Added the following new Design Assistant rules:
- CDC-50001: Missing 1-Bit Synchronizer
- CDC-50002: 1-Bit Synchronized Missing Constraint
- CDC-50003: CE-Type CDC No Constraints
- HRR-10015: High Fan-out Signal
- HRR-10201: Registers Cannot Power Up with Don't Care Logic Level
- HRR-10204: Reset Release Instance Count Check
- RES-30132: Registers May Not Be Properly Reset
- TMC-20500: Hierarchical Tree Duplication was Shallower than Possible
- TMC-20501: Hierarchical Tree Duplication was Shallower than Requested
- TMC-20550: Duplication Candidate Rejected for Placement Constraint
- TMC-20551: Automatically-Discovered Duplication Candidate Likely Requires More Duplication
- TMC-20552: User-Directed Duplication Candidate was Rejected
- TMC-20601: Registers with High Immediate Fan-Out Tension
- TMC-20602: Registers with High Timing Path Endpoint Tension
- TMC-20603: Registers with High Immediate Fan-Out Span
- TMC-20604: Registers with High Timing Path Endpoint Span
- Removed obsolete Design Assistant rules:
- HRR-10014: High Fan-out Nets Driving Clock-Enable Pins
- HRR-10016: Registers Cannot Power-Up With Dont Care Logic Level
- Described new Design Assistant design rule checking tool.
- Added new topics describing each of the Design Assistant rules, under the Recommended Design Practices > Checking for Design Rule Violations section.
- Created subtopics: Clock Region Assignments in Intel Arria 10 and Older Device Families and Clock Region Assignments in Intel Stratix 10 Devices from content in topic: Use Clock Region Assignments to Optimize Clock Constraints.
- Updated topic: Optimizing Timing Closure.
- Updated topic Use Global Clock Network Resources and added topic Use Clock Region Assignments to Optimize Clock Constraints for Intel Stratix 10 support.
- Removed information about Integrated Synthesis.
- Removed information about quartus_drc.
- Implemented Intel rebranding.
- Replaced Internally Synchronized Reset code sample with corrected version.
- Removed information about deprecated physical synthesis options.
- Removed information about unsupported Design Assistant.
- Changed instances of Quartus II to Quartus Prime.
||Updated location of Fitter Settings, Analysis & Synthesis Settings, and Physical Optimization Settings to Compiler Settings.
||Removed references to obsolete MegaWizard Plug-In Manager.
||Removed HardCopy device information.
Removed PrimeTime support.
||Removed survey link.
||Added information to Reset Resources .
- Title changed from Design Recommendations for Altera Devices and the Quartus II Design Assistant.
- Updated to new template.
- Added references to Quartus II Help for “Metastability” on page 9–13 and “Incremental Compilation” on page 9–13.
- Removed duplicated content and added references to Help for “Custom Rules” on page 9–15.
- Removed duplicated content and added references to Quartus II Help for Design Assistant settings, Design Assistant rules, Enabling and Disabling Design Assistant Rules, and Viewing Design Assistant reports.
- Removed information from “Combinational Logic Structures” on page 5–4
- Changed heading from “Design Techniques to Save Power” to “Power Optimization” on page 5–12
- Added new “Metastability” section
- Added new “Incremental Compilation” section
- Added information to “Reset Resources” on page 5–23
- Removed “Referenced Documents” section
- Removed documentation of obsolete rules.
- Changed to 8-1/2 x 11 page size
- Added new section “Custom Rules Coding Examples” on page 5–18
- Added paragraph to “Recommended Clock-Gating Methods” on page 5–11
- Added new section: “Design Techniques to Save Power” on page 5–12
- Updated Figure 5–9 on page 5–13; added custom rules file to the flow
- Added notes to Figure 5–9 on page 5–13
- Added new section: “Custom Rules Report” on page 5–34
- Added new section: “Custom Rules” on page 5–34
- Added new section: “Targeting Embedded RAM Architectural Features” on page 5–38
- Minor editorial updates throughout the chapter
- Added hyperlinks to referenced documents throughout the chapter