2.2.1. Considerations for the Intel® Hyperflex™ FPGA Architecture
While most common techniques of high-speed design apply to designing for the Intel® Hyperflex™ architecture, you must use some new approaches to achieve the highest performance. Follow these general RTL design guidelines to enable the Hyper-Retimer to optimize design performance:
- Design in a way that facilitates register retiming by the Hyper-Retimer.
- Use a latency-insensitive design that supports the addition of pipeline stages at clock domain boundaries, top-level I/Os, and at the boundaries of functional blocks.
- Restructure RTL to avoid performance-limiting loops.
For more information about best design practices targeting Intel® Stratix® 10 devices, refer to the Intel® Stratix® 10 High-Performance Design Handbook.
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