18.104.22.168.2. Selector Multiplexers
Even though the implementation of a tree-shaped, N-input selector multiplexer is slightly less efficient than a binary multiplexer, in many cases the select signal is the output of a decoder. Intel® Quartus® Prime synthesis combines the selector and decoder into a binary multiplexer.
Verilog HDL One-Hot-Encoded CASE Statement
case (sel) 4'b0001: z = a; 4'b0010: z = b; 4'b0100: z = c; 4'b1000: z = d; default: z = 1'bx; endcase
Did you find the information on this page useful?