Intel® Quartus® Prime Pro Edition User Guide: Design Recommendations

ID 683082
Date 8/03/2023
Document Table of Contents

1.3.1. Inferring Multipliers

To infer multiplier functions, synthesis tools detect multiplier logic and implement this in Intel FPGA IP cores, or map the logic directly to device atoms.

For devices with DSP blocks, Intel® Quartus® Prime synthesis can implement the function in a DSP block instead of logic, depending on device utilization. The Intel® Quartus® Prime fitter can also place input and output registers in DSP blocks (that is, perform register packing) to improve performance and area utilization.

The following Verilog HDL and VHDL code examples show that synthesis tools can infer signed and unsigned multipliers as IP cores or DSP block atoms. Each example fits into one DSP block element. In addition, when register packing occurs, no extra logic cells for registers are required.

Verilog HDL Unsigned Multiplier

module unsigned_mult (out, a, b);
	output [15:0] out;
	input [7:0] a;
	input [7:0] b;
	assign out = a * b;
Note: The signed declaration in Verilog HDL is a feature of the Verilog 2001 Standard.

Verilog HDL Signed Multiplier with Input and Output Registers (Pipelining = 2)

module signed_mult (out, clk, a, b);
   output [15:0] out;
   input clk;
   input signed [7:0] a;
   input signed [7:0] b;

   reg signed [7:0] a_reg;
   reg signed [7:0] b_reg;
   reg signed [15:0] out;
   wire signed [15:0] mult_out;

   assign mult_out = a_reg * b_reg;

   always @ (posedge clk)
      a_reg <= a;
      b_reg <= b;
      out <= mult_out;

VHDL Unsigned Multiplier with Input and Output Registers (Pipelining = 2)

USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;

ENTITY unsigned_mult IS
   PORT (
      a: IN UNSIGNED (7 DOWNTO 0);
      b: IN UNSIGNED (7 DOWNTO 0);
      clk: IN STD_LOGIC;
      aclr: IN STD_LOGIC;
      result: OUT UNSIGNED (15 DOWNTO 0)
END unsigned_mult;

ARCHITECTURE rtl OF unsigned_mult IS
   SIGNAL a_reg, b_reg: UNSIGNED (7 DOWNTO 0);
   PROCESS (clk, aclr)
      IF (aclr ='1') THEN
         a_reg <= (OTHERS => '0');
         b_reg <= (OTHERS => '0');
         result <= (OTHERS => '0');
      ELSIF (rising_edge(clk)) THEN
         a_reg <= a;
         b_reg <= b;
         result <= a_reg * b_reg;
      END IF;
END rtl;

VHDL Signed Multiplier

USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;

ENTITY signed_mult IS
   PORT (
      a: IN SIGNED (7 DOWNTO 0);
      b: IN SIGNED (7 DOWNTO 0);
      result: OUT SIGNED (15 DOWNTO 0)
END signed_mult;

ARCHITECTURE rtl OF signed_mult IS
   result <= a * b;
END rtl;