1.1. Using Provided HDL Templates 1.2. Instantiating IP Cores in HDL 1.3. Inferring Multipliers and DSP Functions 1.4. Inferring Memory Functions from HDL Code 1.5. Register and Latch Coding Guidelines 1.6. General Coding Guidelines 1.7. Designing with Low-Level Primitives 1.8. Cross-Module Referencing (XMR) in HDL Code 1.9. Using force Statements in HDL Code 1.10. Recommended HDL Coding Styles Revision History
18.104.22.168. Use Synchronous Memory Blocks 22.214.171.124. Avoid Unsupported Reset and Control Conditions 126.96.36.199. Check Read-During-Write Behavior 188.8.131.52. Controlling RAM Inference and Implementation 184.108.40.206. Single-Clock Synchronous RAM with Old Data Read-During-Write Behavior 220.127.116.11. Single-Clock Synchronous RAM with New Data Read-During-Write Behavior 18.104.22.168. Simple Dual-Port, Dual-Clock Synchronous RAM 22.214.171.124. True Dual-Port Synchronous RAM 126.96.36.199. Mixed-Width Dual-Port RAM 188.8.131.52. RAM with Byte-Enable Signals 184.108.40.206. Specifying Initial Memory Contents at Power-Up
220.127.116.11. If Performance is Important, Optimize for Speed 18.104.22.168. Use Separate CRC Blocks Instead of Cascaded Stages 22.214.171.124. Use Separate CRC Blocks Instead of Allowing Blocks to Merge 126.96.36.199. Take Advantage of Latency if Available 188.8.131.52. Save Power by Disabling CRC Blocks When Not in Use 184.108.40.206. Initialize the Device with the Synchronous Load (sload) Signal
3.4.1. Apply Complete System-Centric Timing Constraints for the Timing Analyzer 3.4.2. Force the Identification of Synchronization Registers 3.4.3. Set the Synchronizer Data Toggle Rate 3.4.4. Optimize Metastability During Fitting 3.4.5. Increase the Length of Synchronizers to Protect and Optimize 3.4.6. Increase the Number of Stages Used in Synchronizers 3.4.7. Select a Faster Speed Grade Device
220.127.116.11. Cross-Probing from Design Assistant to Timing Analyzer
Some Design Assistant rule violations allow cross-probing into Timing Analyzer. For example, for a path that Design Assistant flags with a setup analysis violation due to delay added for hold, you can cross-probe into the Timing Analyzer to view more information on the affected path and edge.
Figure 34. Cross Probing from Design Assistant Rule TMC-20210 Violations to Timing Analyzer
Follow these steps to cross-probe from such Design Assistant rule violations to the Timing Analyzer:
- Compile the design through at least the Compiler's Plan stage.
- Locate a rule violation in the Design Assistant folder of the Compilation Report.
- Right-click the rule violation to display any Report Timing commands available for the violation.
- Click the Report Timing command. The Timing Analyzer opens and reports the timing data for the violation path. Report Timing (Extra Info) includes Estimated Delay Added for Hold and Route Stage Congestion Impact extra data.
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