Intel® Quartus® Prime Pro Edition User Guide: Design Recommendations

ID 683082
Date 8/03/2023
Document Table of Contents

1.4.4. Inferring FIFOs in HDL Code

There are various methods of implementing dual clock FIFOs, depending on the features needed in your design. The following dual clock FIFO example shows the basic FIFO functionality, with a design goal of high speed (fMAX) and small area.

The FIFO supports parameterization up to 32 words deep, and targets memory LABs (MLABs) for its memory block. Synthesis infers the MLABs from behavioral RTL in the generic_mlab_dc module.

Note: If you don’t want to code your own FIFO, you can parameterize the dual clock FIFO IP with the IP parameter editor in the Intel® Quartus® Prime software. Refer to the FIFO Intel FPGA IP User Guide.