184.108.40.206. Simple Shift Register
Intel® Quartus® Prime synthesis implements the register (W = 1 and M = 69) by using the Shift Register Intel® FPGA IP, and maps it to RAM in the device, which may be placed in dedicated RAM blocks or MLAB memory. If the length of the register is less than 69 bits, Intel® Quartus® Prime synthesis implements the shift register in logic.
Verilog HDL Single-Bit Wide, 69-Bit Long Shift Register
module shift_1x69 (clk, shift, sr_in, sr_out); input clk, shift; input sr_in; output sr_out; reg [68:0] sr; always @ (posedge clk) begin if (shift == 1'b1) begin sr[68:1] <= sr[67:0]; sr <= sr_in; end end assign sr_out = sr; endmodule
VHDL Single-Bit Wide, 69-Bit Long Shift Register
LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.all; ENTITY shift_1x69 IS PORT ( clk: IN STD_LOGIC; shift: IN STD_LOGIC; sr_in: IN STD_LOGIC; sr_out: OUT STD_LOGIC ); END shift_1x69; ARCHITECTURE arch OF shift_1x69 IS TYPE sr_length IS ARRAY (68 DOWNTO 0) OF STD_LOGIC; SIGNAL sr: sr_length; BEGIN PROCESS (clk) BEGIN IF (rising_edge(clk)) THEN IF (shift = '1') THEN sr(68 DOWNTO 1) <= sr(67 DOWNTO 0); sr(0) <= sr_in; END IF; END IF; END PROCESS; sr_out <= sr(68); END arch;
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