1.6.8. Counter HDL Guidelines
out <= count_up ? out + 1 : out - 1;
For simple designs, the synthesis engine identifies this coding style and optimizes the logic. However, in complex designs, or designs with preserve pragmas, the Compiler cannot optimize all logic, so more careful coding becomes necessary.
out <= out + (count_up ? 1 : -1);
This style makes more efficient use of resources and area, since it uses only one carry chain adder, and the –1 constant logic is implemented in the LUT before the adder.
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